A probabilistic method for the computation of testability of RTL constructs
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- TL;DR
- Validation of RTL descriptions is a major bottleneck in circuit design, and traditional random simulation methods often face fundamental limitations or prove too expensive.
- Problem
- Certain circuits require a massive number of test vectors to reach hard-to-test constructs and obtain accurate measures of their testability.
- Method
- This work introduces an efficient, static, and non-simulation-based method to determine RTL construct controllability. It takes a Verilog RTL description as input, solves the Chapman-Kolmogorov equations describing the circuit's steady-state, and uses an approximation technique to avoid exponential computational blow-up.
- Results
- The evaluation shows that the proposed approximation method is effective for computing construct controllability and identifying hard-to-control areas in RTL code.
- Contributions
- A static method for computing RTL construct controllability and a technique for leveraging these results to guide random test generation.
- Limitations
- Random simulation methods suffer from fundamental limitations and can be inappropriate or too expensive, necessitating alternative approaches like this static method.
- Takeaways
- The computed controllability values provide accurate feedback to designers and can bias random test generators to achieve higher coverage with fewer vectors.
- Applications
- Circuit design validation and test generation, specifically by biasing random test generators to improve coverage using fewer vectors.
- Topics
- Circuit Design, Functional Validation, RTL Constructs, Probabilistic Methods
- For industry
- Semiconductor and hardware design
- Why it matters
- Improves the efficiency of circuit validation by providing designers with accurate feedback and reducing the vector count needed for test coverage.
Abstract
Validation of RTL descriptions remains one of the principal bottlenecks in the circuit design process. Random simulation based methods for functional validation suffer from fundamental limitations and may be inappropriate or too expensive. In fact, for some circuits, a large number of vector is required in order to make the circuit reach hard to test constructs and obtains accurate values for their testability. In this work, we present a static, non-simulation based, method for the determination of the controllability of RTL constructs that is efficient and gives accurate feedback to the designers in what regards the presence of hard to control constructs in their RTL code. The method takes as input a Verilog RTL description, solves the Chapman-Kolmogorov equations that describe the steady-state of the circuit and outputs the computed values for the controllability of the RTL constructs. To avoid the exponential blow-up that results from writing one equation for each circuit state and solving the resulting system of equations, an approximation method is used. We present results showing that the approximation is effective and describe how the method can be used to bias a random test generator in order to achieve higher coverage using a smaller number of vectors.