DFT and Probabilistic Testability Analysis at RTL
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- TL;DR
- This paper presents probabilistic methods for testability analysis at the Register Transfer Level (RTL) to guide Design-for-Testability (DFT) techniques such as partial-scan and test point insertion (TPI).
- Problem
- Not specified in the abstract.
- Method
- The authors analyze controllability using three approaches: an exact method, an approximation that ignores state variable correlations, and a third that accounts for correlations within pre-defined groups formed using an RTL-based heuristic. Additionally, two observability metrics—event observability and LSA observability—are defined, and a tool is implemented to solve the steady-state Chapman-Kolmogorov equations from a Verilog RTL description.
- Results
- The controllability analysis methods were evaluated using simulation-based controllability as a reference.
- Contributions
- The work introduces novel probabilistic testability analysis methods, two observability metrics, a heuristic for grouping state variables based on RTL information, and a methodology for partial-scan and TPI optimization using testability metrics and a 'DFT dictionary'.
- Limitations
- Not specified in the abstract.
- Takeaways
- The proposed heuristic and optimization methodology were successfully evaluated using the ITC99 benchmark circuits.
- Applications
- Not specified in the abstract.
- Topics
- Hardware Design, Testability Analysis, Design-for-Testability (DFT), Register Transfer Level (RTL)
- For industry
- Not specified in the abstract.
- Why it matters
- Not specified in the abstract.
Abstract
This work presents probabilistic methods for testability analysis at RTL and their use to guide DFT techniques like partial-scan and TPI. Controllability is analyzed using three different approaches, an exact one, an approximated one that ignores the correlation between state variables and a third that only takes into account correlations within pre-defined groups that are formed based on an originally proposed heuristic that uses RTL information. These controllability analysis methods are evaluated using simulation based controllability as a reference. Two observability metrics are originally defined: event observability and LSA observability. The proposed testability analysis methods were implemented in a tool that takes as input a Verilog RTL description, solves the Chapman-Kolmogorov equations that describe the steady-state of the circuit, and outputs the computed values for the testability. A methodology for partial-scan and TPI optimization is proposed. The methodology is based on the testability metrics and on a "DFT dictionary". The proposed heuristic and methodology are evaluated using the ITC99 benchmark circuits