Probabilistic Testability Analysis and DFT Methods at RTL
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- TL;DR
- This research introduces probabilistic methods for analyzing circuit testability at the Register-Transfer Level (RTL) to guide Design-for-Testability (DFT) techniques such as partial-scan and test point insertion (TPI).
- Problem
- Not specified in the abstract.
- Method
- The authors analyze controllability by considering correlations within predefined groups formed via a novel heuristic, and they compute observability at RTL using the Boolean difference. These methods are implemented in a tool that processes Verilog RTL descriptions, solves Chapman-Kolmogorov equations for circuit steady-state, and applies a DFT dictionary-based methodology for partial-scan and TPI optimization.
- Results
- The proposed heuristic and methodology were evaluated using the ITC99 benchmark circuits.
- Contributions
- Not specified in the abstract.
- Limitations
- Not specified in the abstract.
- Takeaways
- Probabilistic testability analysis and optimization techniques can be effectively applied at the RTL using Verilog descriptions and Chapman-Kolmogorov equations, as demonstrated on ITC99 benchmarks.
- Applications
- Not specified in the abstract.
- Topics
- Probabilistic Testability Analysis; DFT Methods
- For industry
- Not specified in the abstract.
- Why it matters
- Not specified in the abstract.
Abstract
This work presents probabilistic methods for testability analysis at RTL and their use to guide DFT techniques like partial-scan and TPI. Controllability is analyzed using an approach that takes into account correlations within pre-defined groups formed based on an originally proposed heuristic. A method for observability computation at RTL based on the Boolean difference is presented. These testability analysis methods were implemented in a tool that reads a Verilog RTL description, solves the Chapman-Kolmogorov equations that describe the steady-state of the circuit, and outputs the computed values for the testability. A methodology for partial-scan and TPI optimization is proposed and implemented. The methodology is based on the testability metrics and on a "DFT dictionary". The proposed heuristic and methodology are evaluated using the ITC99 benchmark circuits