Implicit FSM decomposition applied to low-power design
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- TL;DR
- A clock-gating technique based on finite-state machine (FSM) decomposition is proposed to reduce switching activity and power consumption in sequential logic circuits.
- Problem
- Traditional explicit methods for FSM decomposition require time and space exponential to the number of registers in the circuit, limiting their applicability to relatively small circuits.
- Method
- The approach computes two functionally equivalent sub-FSMs where the clock for one sub-FSM is disabled during transitions in the other. To minimize average switching activity, a small cluster of states with high stationary state probability is used to create the smaller sub-FSM, with decomposition performed implicitly through direct manipulation of the circuit.
- Results
- Experiments show that power consumption can be substantially reduced, in some cases by more than 70%.
- Contributions
- An implicit FSM decomposition technique for low-power design that avoids the exponential complexity limitations of explicit state transition graph manipulation.
- Limitations
- Not specified in the abstract.
- Takeaways
- Implicit FSM decomposition enables effective clock-gating for sequential logic circuits, achieving substantial power reductions.
- Applications
- Low-power design of sequential logic circuits and digital hardware.
- Topics
- Clock-gating; Finite-State Machine (FSM) decomposition; Low-power design; VLSI systems
- For industry
- Semiconductor and digital hardware design
- Why it matters
- Not specified in the abstract.
Abstract
Clock-gating techniques are very effective in the reduction of the switching activity in sequential logic circuits. In this paper, we describe a clock-gating technique based on finite-state machine (FSM) decomposition. The approach is based on the computation of two sub-FSMs that together have the same functionality as the original FSM. For all the transitions within one sub-FSM, the clock for the other sub-FSM is disabled. To minimize the average switching activity, we search for a small cluster of states with high stationary state probability and use it to create the small sub-FSM. Explicit manipulation of the state transition graph requires time and space exponential on the number of registers in the circuit, thereby restricting the applicability of explicit methods to relatively small circuits. The approach we propose is based on a method that implicitly performs the FSM decomposition. Using this technique, the FSM decomposition is performed by direct manipulation of the circuit. We provide a set of experiments that show that power consumption can be substantially reduced, in some cases by more than 70%.