conference · 1998
Finite state machine decomposition for low power
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- TL;DR
- This paper presents a new clock-gating technique based on finite state machine (FSM) decomposition to reduce switching activity in sequential logic circuits.
- Problem
- Not specified in the abstract.
- Method
- The authors compute two sub-FSMs that share the functionality of the original FSM, disabling the clock for one sub-FSM during transitions in the other. To minimize average switching activity, they identify a small cluster of states with high stationary state probability to form the smaller sub-FSM.
- Results
- Not specified in the abstract.
- Contributions
- Not specified in the abstract.
- Limitations
- Not specified in the abstract.
- Takeaways
- This approach keeps a small amount of logic active most of the time while disabling a much larger circuit.
- Applications
- Not specified in the abstract.
- Topics
- Not specified in the abstract.
- For industry
- Not specified in the abstract.
- Why it matters
- Not specified in the abstract.
Abstract
Clock-gating techniques have been shown to be very effective in the reduction of the switching activity in sequential logic circuits. In this paper we describe a new clock-gating technique based on finite state machine (FSM) decomposition. We compute two sub-FSMs that together have the same functionality as the original FSM. For all the transitions within one sub-FSM, the clock for the other sub-FSM is disabled. To minimize the average switching activity, we search for a small cluster of states with high stationary state probability and use it to create the small sub-FSM. This way we will have a small amount of logic that is active most of the time, during which is disabling a much larger circuit, the other sub-FSM.