Summary AI-generated
- TL;DR
- A testing methodology for digital VLSI circuits is introduced, relying on realistic fault lists tailored to specific manufacturing processes, technologies, and integrated circuit layouts.
- Problem
- Not specified in the abstract.
- Method
- Automatic fault listing is performed using a hierarchical layout-to-fault extractor called LIFE, while test-pattern validation is handled by an accurate switch-level fault simulator with timing capabilities named SWIFT. Fault-list compression is also applied based on user-defined objectives.
- Results
- Not specified in the abstract.
- Contributions
- Not specified in the abstract.
- Limitations
- Not specified in the abstract.
- Takeaways
- The developed software tools are currently being integrated into the ICD tool box within a workstation-based IC design environment.
- Applications
- The methodology and its corresponding software tools can be applied in both integrated circuit design and production testing environments.
- Topics
- Not specified in the abstract.
- For industry
- Integrated circuit design and manufacturing.
- Why it matters
- Not specified in the abstract.
Abstract
A testing methodology for digital VLSI circuits is proposed that is based on the definition of a realistic fault list, which depends on the technology, the manufacturing process, and the IC layout. Automatic fault listing is carried out by a hierarchical layout-to-fault extractor, LIFE. Fault-list compression is performed according to user-defined fault listing objectives. Test-pattern validation is made by an accurate switch-level fault simulator with timing information capabilities, SWIFT. The methodology and the correspondent software tools can be used in the IC design and production testing environments. At present, the two software tools are to be included in the ICD tool box, in a workstation-based IC design environment.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">></ETX>