Sensitivity to SEUs evaluation using probabilistic testability analysis at RTL
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- TL;DR
- This research presents probabilistic methods for testability analysis at the Register Transfer Level (RTL) to evaluate how sensitive digital circuits are to Single Event Upsets (SEUs).
- Problem
- Not specified in the abstract.
- Method
- The study introduces 'event detectability,' a new probabilistic testability metric combining event observability and controllability. These methods were implemented in a tool called ASCOPA, which takes a Verilog RTL description as input and solves Chapman-Kolmogorov equations to compute the metrics.
- Results
- The proposed metric successfully evaluates whether circuit changes caused by SEUs are ignored or propagated by the circuit's dynamic behavior, and it establishes a relationship between static and dynamic SEU cross-sections for ITC'99 benchmark circuits.
- Contributions
- Not specified in the abstract.
- Limitations
- Not specified in the abstract.
- Takeaways
- For the b04 benchmark circuit, the error probability can be reduced by 50% by using radiation-hardened registers on only one-third of the circuit.
- Applications
- Not specified in the abstract.
- Topics
- Hardware reliability, probabilistic testability analysis, and fault tolerance
- For industry
- Not specified in the abstract.
- Why it matters
- Not specified in the abstract.
Abstract
This work presents probabilistic methods for testability analysis at RTL and their use to evaluate the sensitivity of a digital circuit to Single Event Upsets (SEUs). A new probabilistic testability metric is proposed, in order to evaluate if the possible changes caused by SEUs are ignored or propagated by the dynamic behavior of the circuit. The new metric, event detectability, is defined based on the recently proposed event observability metric combined with the controllability. A methodology for error rate prediction based on the new metric is proposed. The testability analysis methods were implemented in a tool (ASCOPA) that takes as input a Verilog RTL description, solves the Chapman-Kolmogorov equations that describe the steady-state of the circuit, and outputs the computed values for the testability metrics. The proposed metric is used to obtain the relation between the static and the dynamic SEUs cross-section for ITC'99 benchmark circuits. It is shown that the error probability, for the b04 benchmark, can be 50% reduced using only 1/3 of radiationhardened registers.