conference · 1999
Robust techniques for watermarking sequential circuit designs
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- TL;DR
- This paper presents a methodology for watermarking synchronous sequential circuits to protect and identify the authorship of hardware designs.
- Problem
- Not specified in the abstract.
- Method
- The approach embeds a digital watermark directly into the state transition graph of the circuit.
- Results
- Not specified in the abstract.
- Contributions
- Not specified in the abstract.
- Limitations
- Not specified in the abstract.
- Takeaways
- The methodology is designed for sequential circuits provided as firm Intellectual Property (IP), such as structural descriptions and circuit netlists.
- Applications
- Not specified in the abstract.
- Topics
- Not specified in the abstract.
- For industry
- Not specified in the abstract.
- Why it matters
- Not specified in the abstract.
Abstract
We present a methodology for the watermarking of synchronous sequential circuits that makes it possible to identify the authorship of designs by imposing a digital watermark on the state transition graph of the circuit. The methodology is applicable to sequential designs that are made available as firm Intellectual Property (IP), the designation commonly used to characterize designs specified as structural descriptions or circuit netlists.