conference · 2002

Circuit partitioning techniques for power estimation using the full set of input correlations

Ana T. Freitas, Arlindo L. Oliveira · 6 citations

View original publication →

See where this sits in the topic map →

Summary AI-generated

TL;DR
Accurate logic-level power estimation requires accounting for all input correlations, which can now be achieved through an efficient probabilistic approach.
Problem
While this probabilistic method can compute exact power dissipation using statistics that would otherwise demand extremely large simulation traces, its applicability has been limited to very small circuits.
Method
This paper introduces a circuit partitioning technique that accelerates the estimation algorithm by avoiding the need to compute global BDD representations for node functions.
Results
The proposed partitioning approach successfully extends the range of circuits that can be analyzed while maintaining the full set of input correlations and incurring no loss in accuracy.
Contributions
Not specified in the abstract.
Limitations
Not specified in the abstract.
Takeaways
Circuit partitioning makes it possible to apply exact, correlation-aware power estimation to a much wider range of circuits without sacrificing accuracy.
Applications
Not specified in the abstract.
Topics
Not specified in the abstract.
For industry
Not specified in the abstract.
Why it matters
Not specified in the abstract.

Abstract

Exact power estimation, at logic level, is only possible if all the input correlations are taken into account. Recently, a probabilistic approach that uses a simple but powerful formalism for power estimation taking into account all the input correlations has been proposed. With this probabilistic approach it is possible to compute exactly the power dissipation of combinational modules using input statistics that would require extremely large traces if simulation based methods were to be used. However, the applicability of the method is limited to very small circuits. This paper describes a circuit partitioning technique that speeds up that method. By using partitioning techniques we avoid the computation of global BDD representations for node functions, thereby extending considerably the range of applicability of the algorithm. Moreover, the partitioning maintains the full set of correlations and, therefore, does not induce any loss of accuracy.

References within the group

Cited by (group publications)

← All publications